Field
The technology relates to integrated circuit fabrication, and more particularly to placement, routing, and optimization of an integrated circuit design that obeys rules that specify the relative placement of circuit elements.
Description of Related Art
An integrated circuit design flow typically proceeds through the following stages: product idea, EDA software, tapeout, fabrication equipment, packing/assembly, and chips. The EDA software stage includes the steps shown in the following table:
EDA step What HappensSystem Design Describe the functionality to implement What-if planning Hardware/software architecture partitioning Logic Design and Write VHDL/Verilog for modules in system Functional Check design for functional accuracy, does the Verification design produce correct outputs? Synthesis and Translate VHDL/Verilog to netlist Design for Test Optimize netlist for target technology Design and implement tests to permit checking of the finished chip Design Planning Construct overall floor plan for the chip Analyze same, timing checks for top-level routing Netlist Verification Check netlist for compliance with timing constraints and the VHDL/Verilog Physical Placement (positioning circuit elements) and Implement. routing (connecting circuit elements) Analysis and Verify circuit function at transistor level, allows Extraction for what-if refinement Physical Various checking functions: manufact., electrical, Verfication (DRC, lithographic, circuit correctnessLRC, LVS) Resolution Geometric manipulations to improve Enhanc. (OPC, manufacturability PSM, Assists) Mask Data “Tape-out” of data for production of masks for Preparation lithographic use produce finished chips
With regard to physical implementation technology, methodologies for structured placement offer circuit designers superior power, yield, and/or area for a given logic function. With the advent of manual placement of transistors, designers created arrayed layouts where logic gates were manually placed in a regularized fashion. This methodology has evolved to the point that automation has been applied to the problem. However, regularized placement still suffers from a great deal of manual effort, such as in cell drive strength selection.
Capturing a priori designer knowledge of structured placement requirements in HDL is a nontrivial problem. Even if captured, structured placement requirements are lost during standard cell random placement. Standard cell placers tend to take more localized views during optimization. This results in not just loss of regularity, but also extra buffering, routing, vias, and cell oversizing, compared to a solution which might be obtained following structured placement.
One approach to this problem is to perform cell sizing and optimization of a structured placement manually through homegrown tools. This approach is quite expensive in terms of engineering effort. This approach is also hard to integrate with the rest of the design. Such integration requires multiple iterations, because standard cell placement and optimization changes the placement, sizing, etc. of the surrounding, non-structured logic. Unfortunately, this triggers another iteration, with further manual sizing and optimization efforts through the homegrown tools for the block with structured placement.
Other approaches to this problem are to generate structured placement through synthesis or through a specific tool, and then pass on the result to a placer through a set of special constraints, or as a macro/IP block. The initial structure generated through synthesis or through the special tool is problematic. Because the initial structure is generated prior to placement, the initial structure is formed lacking complete placement knowledge, and thus the initial structure fails to lead to optimal placement as generation. Also if it is passed as a macro/IP block, then place and route tools cannot resize or otherwise optimize the blocks.
Relative placement rules as applied to clock trees are problematic. Several of the disadvantages follow. Relative placement rules specified in a scripting language such TCL can require updates as the relative placement language changes. The design can be over-constrained and more clock gates inserted than needed, and clock gate incorrectly sized. A manual iterative process of figuring the maximum distance of the flip-flops to cluster is labor intensive. There can be inability to cluster and create smaller relative placement groups when a clock gate drives more than the maximum fanout limit of a clock gate. It is labor intensive to manually create relative placement rules and manually modify the netlist (connect/disconnect gates/flops) and insert clock buffers and create relative placement structures. Non-convergence can be caused by using ad-hoc/distance based techniques up front in placement/optimization versus a native clock tree clustering algorithm used in clock tree synthesis, as they are not the same processes.
Therefore, it would be desirable to efficiently implement structured placement with circuit design.